ICEPIK – Lattice ICE40UL1K on a 8-pin PDIP PCB
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Lattice ICE40UL1K-SWG16 FPGA (WLCSP-16 package)
Onboard +1v2 LDO powers FPGA
8-pin PDIP format for ease of use (2.54mm hole pitch / 0.1″ spacing)
User defined VIO rail (typical +3v3)
Boot custom RTL code from CRAM (static ram), external FLASH or internal OTP
OTP program / debug your custom IP with the Axxon ICE-TRAY Programmer
Fully compatible with Lattice ICE CUBE, DIAMOND and open source tool chains
Program in Verilog or VHDL
Low cost and convenient to use
Designed & Assembled in Canada